1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a divided word line structure in which word lines are divided into main word lines and sub-word lines. More specifically, the present invention relates to an arrangement for driving a sub-word line to a selected state.
2. Description of the Background Art
FIG. 11 is a schematic representation of a configuration of an array portion of a conventional semiconductor memory device. In FIG. 11, memory cells MC are arranged in a matrix of rows and columns. A sub-word line is provided correspondingly to each row of memory cells MC. Sub-word lines SWL00, SWL01, SWL10, SWL11 are shown in FIG. 11. Memory cells MC are divided into blocks along the row direction, and sub-word lines SWL are arranged in the respective blocks. A main word line ZMWL is provided in common to these sub-word lines. Sub-word line drivers SWD00, SWD01, SWD10, SWD11 are provided to sub-word lines SWL00, SWL01, SWL10, SWL11, respectively. Each of these sub-word line drivers SWD00, SWD01, SWD10, SWD11 drives a corresponding sub-word line to the selected state according to the signal potential on main word line ZMWL and a row select signal RSL. Row select signal RSL includes complementary signals SD and ZSD, and designates a sub-word line in a set of sub-word lines aligned in the column direction. Thus, row select signal RSL (sub-decode signals SD and ZSD) designates one of sub-word lines SWL00 and SWL10, and one of sub-word lines SWL01 and SWL11.
By providing one main word line ZMWL to a plurality of rows of memory cells, the pitch condition of main word line ZMWL is mitigated. Only the sub-word line drivers are connected to main word line ZMWL, and memory cells MC are not connected to main word line ZMWL. Thus, the load (impedance) on main word line ZMWL can be reduced, and the word line can be driven to the selected state at a high speed. Such an arrangement in which word lines are divided into main word lines ZMWL and sub-word lines SWL (generically indicating sub-word lines SWL00, SWL01, SWL10, SWL11) is referred to as a divided word line structure.
Moreover, a bit line pair BLP is shown in FIG. 11. Bit line pair BLP includes complementary bit lines BL and /BL, and a memory cell MC is connected to one of bit lines BL and /BL.
FIG. 12 is a diagram representing a configuration of sub-word line driver SWD shown in FIG. 11. Referring to FIG. 12, sub-word line driver SWD includes a P-channel MOS transistor Q1 that is rendered conductive, when the signal potential on main word line ZMWL is at a ground voltage Vss level, to transmit a sub-decode signal SD onto sub-word line SWL, an N-channel MOS transistor Q2 that is rendered conductive, when the signal potential on main word line ZMWL is at a high voltage Vpp, to drive sub-word line SWL to ground voltage Vss level, and an N-channel MOS transistor Q3 that is rendered conductive, when sub-decode signal ZSD is at an array power-supply voltage Vdda level, to drive sub-word line SWL to ground voltage Vss level.
Sub-decode signal SD changes between high voltage Vpp and ground voltage Vss, and sub-decode signal ZSD changes between array power-supply voltage Vdda and ground voltage Vss. High voltage Vpp is transmitted to sub-word line SWL by sub-decode signal SD for the reason given below.
As shown in FIG. 12, a memory cell MC includes a memory capacitor MQ for storing information, and an access transistor MT rendered conductive in response to the signal potential on sub-word line SWL to connect memory capacitor MQ to bit line BL (or /BL). Access transistor MT is formed by an N-channel MOS transistor. Therefore, when writing into memory capacitor MQ logic high or xe2x80x9cHxe2x80x9d level (array power-supply voltage Vdda level) data, there is a need to prevent the voltage level of the xe2x80x9cHxe2x80x9d level data of memory capacitor MQ from being lowered by threshold voltage loss in access transistor MT. In order to compensate for the threshold voltage loss, high voltage Vpp higher than array power-supply voltage Vdda is transmitted on sub-word line SWL. In order to reliably set P-channel MOS transistor Q1 to the off state, that main word line ZMWL is driven to high voltage Vpp level.
With the arrangement of sub-word line driver SWD shown in FIG. 12, MOS transistor Q1 attains the off state while MOS transistor Q2 attains the on state when main word line ZMWL is at high voltage Vpp level so that MOS transistor Q2 drives sub-word line SWL to ground voltage Vss level regardless of the logic levels of sub-decode signals SD and ZSD. When main word line ZMWL is at high voltage Vpp level of the non-selected state, sub-word line SWL also is held at ground voltage Vss level of the non-selected state.
On the other hand, when main word line ZMWL is driven to ground voltage Vss level of the selected state, MOS transistor Q1 attains either the off or on state while MOS transistor Q2 attains the off state. When sub-decode signal SD is at high voltage Vpp level, MOS transistor Q1 attains the on state so that the sub-decode signal of high voltage Vpp level is transmitted on sub-word line SWL. When sub-decode signal SD is at ground voltage Vss level of the non-selected state, MOS transistor Q1 attains the off state, with its gate and its source being at the same voltage level. In this state, both MOS transistors Q1 and Q2 attain the off state. Sub-decode signal ZSD at this time is at array power-supply voltage Vdda level, and MOS transistor Q3 attains the on state, driving sub-word line SWL to ground voltage Vss level. Thus, the use of complementary sub-decode signals SD and ZSD prevents sub-word line SWL from electrically floating.
FIG. 13 is a diagram representing a configuration of a conventional sub-decode signal generating portion. In FIG. 13, the sub-decode signal generating portion includes a sub-decoder 900 for generating a sub-decode fast signal ZSDF according to a predecode signal X, and a sub-decode signal generating circuit 910 for generating complementary sub-decode signals (word line designating signal) from sub-decode fast signal ZSDF.
Sub-decoder 900 includes a P-channel MOS transistor 901 connected between a high voltage node receiving a high voltage Vpp and a node 902 and receiving a reset signal ZRSET at a gate thereof, and an N-channel MOS transistor 903 connected between node 902 and a ground node and receiving predecode signal X at a gate thereof Reset signal ZRSET changes between high voltage Vpp and ground voltage Vss. Predecode signal X changes between peripheral power-supply voltage Vddp and ground voltage Vss.
Sub-decode signal generating circuit 910 includes an inverter 911 for receiving sub-decode fast signal ZSDF to generate sub-decode signal SD, and an inverter 912 for receiving an output signal from inverter 911 to generate a complementary sub-decode signal ZSD. Inverter 911 receives high voltage Vpp as one operating power-supply voltage, while inverter 912 receives array power-supply voltage Vdda as one operating power-supply voltage. Therefore, sub-decode signal SD has an amplitude of high voltage Vpp, and the complementary sub-decode signal ZSD has an amplitude of array power-supply voltage Vdda. Now, the operation of the sub-decode signal generating portion shown in FIG. 13 will be described.
At a standby state, reset signal ZRSET is at ground voltage Vss level and predecode signal X is also at ground voltage Vss level. Therefore, node 902 is charged to high voltage Vpp level by MOS transistor 901 in the on state.
Sub-decode signal SD attains the ground voltage level of the logic low or xe2x80x9cLxe2x80x9d level, and the complementary sub-decode signal ZSD attains array power-supply voltage Vdda level of the logic high or xe2x80x9cHxe2x80x9d level. Thus, in sub-word line driver SWD shown in FIG. 12, MOS transistor Q3 is in the on state (and main word line ZMWL is at high voltage Vpp level), and sub-word line SWL is maintained at the ground voltage level.
When an active cycle for selecting a memory cell starts, reset signal ZRSET attains high voltage Vpp level and MOS transistor 901 attains the off state. Predecode signal X, in the selected state, attains peripheral power-supply voltage Vddp level of the xe2x80x9cHxe2x80x9d level, and sub-decode fast signal SDF from node 902 is driven to ground voltage Vss level by MOS transistor 903. Accordingly, sub-decode signal SD attains high voltage Vpp level, and the complementary sub-decode signal ZSD attains ground voltage Vss level. Two stages of cascaded inverters 911 and 912 are utilized to generate from sub-decode fast signal ZSDF, sub-decode signals SD and ZSD that are complementary to one another and have different amplitudes, so that the circuit area can be reduced. Moreover, by setting the amplitude of the complementary sub-decode signal ZSD to array power-supply voltage Vdda level, the lower power consumption can be achieved than the case where high voltage Vpp is used. Further, array power-supply voltage Vdda can stabilize the voltage level of the complementary sub-decode signal ZSD.
FIG. 14 is a schematic representation of the input and output characteristics of inverter 912 shown in FIG. 13. In FIG. 14, an input signal SD is indicated on the horizontal axis and an output signal ZSD is indicated on the vertical axis. High voltage Vpp is at 3.6V, for instance, and array power-supply voltage Vdda is at 2.0V, for instance. An input logic threshold voltage Lth of inverter 912 is set at a relatively high value, since the amplitude of input signal (sub-decode signal) SD is high voltage Vpp and is greater than the amplitude of output signal ZSD of inverter 912. This is done to equalize the rise time and the fall time of the complementary sub-decode signal ZSD upon the change of the input signal of inverter 912.
High voltage Vpp is consumed in the sub-decode signal generating circuit for generating a sub-decode signal and in a main word line drive circuit (not shown) for driving a main word line. During the operation of selecting a word line, if the voltage level of high voltage Vpp falls and nears input logic threshold voltage Lth of inverter 912, the voltage level of the complementary sub-decode signal ZSD from inverter 912 rises. When the voltage level of the complementary sub-decode signal ZSD from inverter 912 rises and becomes higher than a threshold voltage Vth of MOS transistor Q3 in sub-word line driver SWD as shown in FIG. 15, MOS transistor Q3 is rendered conductive.
When main word line ZMWL is in the selected state of ground voltage Vss level, if sub-decode signal SD is at the xe2x80x9cHxe2x80x9d level, its complementary sub-decode signal ZSD also attains the high level. MOS transistors Q1 and Q3 are rendered conductive, causing a through current to flow through MOS transistors Q1 and Q3, which leads to an increase in the consumed current. In addition, high voltage Vpp is consumed due to this through current during a normal operation mode, and when the voltage level of high voltage Vpp is lowered, the voltage level of the selected sub-word line SWL is lowered as well, which creates the possibility that the xe2x80x9cHxe2x80x9d level data of a sufficient voltage level may not be written into a memory cell.
In particular, in a test mode such as a wafer burn-in test, all word lines (sub-word lines), or half the word lines (sub-word lines) with odd number addresses or even number addresses are selected at once. When such a plurality of word lines (sub-word lines) are selected at the same time and more word lines (sub-word lines) than those selected in the normal operation mode are selected, more supplied charges from a high voltage generating circuit are consumed, and the degree of fall in high voltage Vpp becomes greater (since the number of selected sub-word lines increases and the number of the paths of through currents increases). If all of or more than the supplied charges from the high voltage generating circuit are consumed upon such fall in high voltage Vpp level, the voltage level of high voltage Vpp would retain the lowered state, and consequently, a high voltage of the intended level cannot be applied to the selected word lines (main and sub-word lines), the voltage stress acceleration cannot be performed with accuracy, and the reliability of the products (chips) cannot be ensured even with a burn-in test.
An object of the present invention is to provide a semiconductor memory device in which no through current is generated even when the voltage level of high voltage Vpp becomes lower.
Another object of the present invention is to provide a semiconductor memory device that can reliably maintain the complementary sub-decode signal in the non-selected state even when the voltage level of high voltage Vpp becomes lower.
A further object of the present invention is to provide a semiconductor memory device that allows an accurate voltage application in a voltage stress acceleration test such as a burn-in test.
Briefly, the semiconductor memory device according to the present invention generates a complementary sub-decode signal in different circuitry from a circuit utilizing a high voltage. In other words, the complementary sub-decode signals are produced via separate paths.
By generating complementary sub-decode signals via separate paths, the logic voltage levels of the complementary sub-word line select signals can be prevented from affecting one another, and the complementary sub-word line select signals (sub-decode signals) can be reliably fixed to voltages of different logic levels.